1. Field of the Invention
The present Invention relates to a method of producing an insulated gate semiconductor element or other semiconductor devices, such as a thin film transistor (TFT) having a non-single crystalline silicon film, and particularly to a doping method for controlling a threshold value voltage. The present invention is applied to a semiconductor device formed on an insulating substrate made of glass or the like, or on a semiconductor substrate made of single crystal silicon, etc.
2. Description of the Related Art
A doping technique applied to a semiconductor material has three main effects described below.
1) Doping to the source and drain regions of a transistor.
A purpose of doping the source and drain regions of a transistor formed on a semiconductor material (for example, implanting phosphorus or boron in silicon) is to produce carriers (electrons or holes) in the semiconductor material, to thereby remarkably increase an on-current of the transistor. In producing an n-type semiconductor region by implanting phosphorus in the source and drain regions of the TFT, n-type semiconductor region that allows the TFT to operate cannot be formed without implanting phosphorus in the semiconductor material at 1.times.10.sup.19 to 1.times.10.sup.21 atoms/cm.sup.3.
2) Doping to the channel region of a transistor.
A technique of doping the channel region of a transistor is has been widely known and is called "channel dope". This is used in practice to control a threshold voltage value "V.sub.th ". V.sub.th of an intrinsic semiconductor material is originally 0 V. However, there is a case in which V.sub.th is shifted from 0 for the reason that the semiconductor material is processed to improve the crystallinity or homogeneity of the semiconductor material, or for other reasons. The channel dope allows such a shift of V.sub.th to return to 0 V.
When V.sub.th is shifted to the minus side, p-type ions, e.g., boron ions are implanted as a dopant to make V.sub.th shift to the plus side. When V.sub.th is shifted to the plus side, n-type ions, e.g., phosphorus ions are implanted as a dopant to make V.sub.th shift to the minus side. It is required that the dose of impurity ions to be implanted is properly adjusted in accordance with the degree of shift of V.sub.th. In general, the dose of impurity ions implanted in the channel region is smaller than that implanted in the source and drain regions.
3) Doping to the LDD (lightly doped drain) region of a transistor.
An LDD technique has such effects that the deterioration of a transistor is prevented or an off-current is reduced. In the LDD technique, LDD regions are formed between source and drain regions and a channel region, and the dose smaller than that implanted in the source and drain regions is implanted in the LDD regions. Thus, the LDD regions having an intermediate characteristic in the physical property (mainly the electric physical property) between the source and drain regions and the channel region are formed. This causes one cushion to be produced in a difference in the physical property between the source/drain regions and the channel region. Therefore, the off-current is reduced, and the deterioration of the transistor characteristic is suppressed.
The main effects of doping are described above. A large amount of dopant is implanted in the semiconductor material to thereby form a lattice defect. In general, a doped region is made amorphous. Hence, in general, an annealing process is required to repair the lattice defect after doping.
(Process for attaining the present invention)
A method by which a TFT having a crystalline silicon film formed on a glass substrate is produced at a low temperature has been demanded. This is required to obtain the active matrix liquid crystal display at the low production costs.
Recently, insulated gate semiconductor devices having a thin film shaped active layer (also called "an active region") on an insulating substrate have been researched. In particular, thin film shaped insulated gate transistors, so-called TFT have been researched eagerly. They are classified into an amorphous silicon TFT, a crystalline silicon TFT and so on, depending on the material or the crystal state of a semiconductor to be used. The crystalline silicon is directed to non-single crystal which is not of single crystal. Thus, they are generally called a non-single crystal silicon TFT.
In general, a semiconductor in an amorphous state has a small electric field mobility and cannot be used for a TFT requiring a high speed operation. Since amorphous silicon has a remarkable small p-type electric field mobility, it cannot be formed into a p-channel TFT (PMOS TFT), and amorphous silicon cannot be formed into a complementary MOS (CMOS) circuit in combination with an n-channel TFT (NMOS TFT).
A crystalline semiconductor is larger in electric field mobility than an amorphous semiconductor, to enable a high speed operation. Since crystalline silicon can be formed into NMOS TFT as well as PMOS TFT, a CMOS circuit can be produced.
To obtain a crystalline silicon film, it is required that an amorphous silicon film formed by plasma CVD is heated at 600.degree. C. or higher for several tens hours or longer. However, when a glass substrate is normally exposed to 600.degree. C. or higher for a long time, it cannot be used as a substrate for forming a thin film semiconductor device formed by a semiconductor thin film having a thickness of about several hundreds .ANG. because of remarkable deformation (distortion) or shrinkage. Although there exists a glass substrate that withstands a high temperature of 600.degree. C. or higher, it is expensive and greatly causes the production costs to increase.
A known example of low temperature crystallizing techniques is of a technique by which an amorphous silicon film is crystallized by the irradiation of a laser light. However, since it requires a high output laser beam over a large area, there arises a problem from the viewpoints of the production costs and the productivity. Also, when a crystalline silicon film is obtained by only the irradiation of a laser light, the characteristics are dispersed.
What is required under such a condition is a technique in which a crystalline silicon film is obtained by a heat treatment at a temperature which can be withstood by the glass substrate. In such a technique, as disclosed in Japanese Patent Unexamined Publication Nos. 6-232059 and 6-244104 by the present applicant, a crystalline silicon film can be obtained by thermal annealing at a lower temperature for a shorter period of time than a usual case by using such an effect that elements such as nickel, iron, cobalt, platinum or palladium (hereinafter referred to as "crystallization catalyst element or simply "catalyst element") promotes the crystallization of amorphous silicon. When nickel is used as a catalyst element, a crystalline silicon film can be obtained by thermal annealing at about 550.degree. C. for about 4 hours.
The like technique is disclosed in Japanese Patent Unexamined Publication Nos. 6-318701 and 6-333951 and so on. It is found that, in the silicon film having such a crystallization catalyst element, an impurity element in an impurity region of source/drain regions or the like which is formed by the irradiation and implantation of n-type or p type impurity ions by ion doping or the like can be activated by thermally annealing at a lower temperature than that of a conventional method (Japanese Patent Unexamined Publication Nos. 6-267980 and 6-267989). To achieve the above, it is preferable that the concentration of catalyst elements is 1.times.10.sup.15 to 1.times.10.sup.19 atoms/cm.sup.3.
In a lower concentration that does not reach the above range, the crystallization cannot be promoted whereas in a higher concentration that exceeds the above range, it adversely affects the silicon semiconductor characteristic. The concentration of the catalyst elements in this case is of a value analyzed by the secondary ion mass spectrometry (SIMS), and in most of cases, the catalyst elements have a distribution in a film, and the above value denotes a lowest value of the catalyst elements in the silicon film.
However, it is frequently observed that a threshold value voltage is shifted in the semiconductor device produced using crystalline silicon. In most of cases, the threshold value voltage is shifted in a negative direction, but there is some cases where it is shifted in a positive direction. In a device using a coating formed by the vapor growth method such as plasma CVD with tetraethoxysilane (TEOS, chemical formula Si(OC.sub.2 H.sub.5)) as a gate insulating film, most of the threshold value voltage are shifted in the negative direction. Also, it is observed that even in the crystalline silicon film obtained using a catalyst element, the threshold value is shifted in the negative direction.
It is assumed that the above phenomenon is derived from a defect existing between a silicon film and a gate insulating film, an impurity (carbon, nitrogen, etc.) in the gate insulating film, a localized center, etc. In the crystalline silicon film using a catalyst metal element, that V.sub.th is shifted in the negative direction means that a channel forming region becomes the n-type even with a difference of some degree. A variety of metal elements can be recited as an element that puts a silicon semiconductor into a weak n-type (in other words, it can exhibit the state of putting it into the weak n-type). Hence, it is concluded that a cause of putting it into the n-type is a metal element introduced for promoting the crystallization.
As described in the above conventional example, the threshold value voltage can be controlled by doping a semiconductor with a very small amount of n-type or p-type impurity. Thus, it has been expected that the like technique could be applied even to the semiconductor device using crystalline silicon, and such application has been tried. However, the threshold voltage value has been hardly improved.
That is, in the conventional semiconductor integrated circuit technique, an ion having the n-type or p-type impurity at a required amount are accelerated and implanted into the semiconductor. After that, the crystal property is recovered and the implanted impurity is activated, by thermal annealing (500.degree. C. or higher, normally about 1000.degree. C.). However, when the same method is applied to the crystalline silicon film, the threshold value does not fluctuate at all when the concentration of the impurity is 1.times.10.sup.18 atoms/cm.sup.3 or less, but it fluctuates rapidly with a boundary of 1.times.10.sup.18 atoms/cm.sup.3 and becomes the n-type or p-type substantially. This cannot be used in a channel of a TFT or the like.
In amorphous silicon, there has been known that a small amount of n-type or p-type impurity is added to the semiconductor at forming a film, thereby being capable of controlling the threshold value. Thus, an attempt has been made to form a crystalline silicon film using an amorphous silicon film to which a small amount of impurity is added in the same manner. However, similarly even in this case, the threshold value does not fluctuate at all when the concentration of the impurity is 1.times.10.sup.18 atoms/cm.sup.3 or less, but it. fluctuates rapidly with a boundary of 1.times.10.sup.18 atoms/cm.sup.3, an intermediate threshold value cannot be obtained.
The above phenomenon completely difters from such a phenomenon that the threshold value fluctuates continuously gently by adding the impurity at a concentration of 1.times.10.sup.15 to 1.times.10.sup.18 atoms/cm.sup.3, as observed in the conventional semiconductor integrated circuit technique or the amorphous silicon technique. It has been considered that it is impossible to control the threshold value in the crystalline silicon because of this phenomenon.
When V.sub.th is shifted to the negative side, the power of the gate electrode and the semiconductor region in the TFT has a large difference between the devices. This leads to a serious drawback in the TFTs arranged in the form of a pixel matrix. Thus, it is necessary that boron is added to the channel forming region to adjust V.sub.th to 0 V.